1. Field of the Invention
This invention relates to an analog delay circuit and a clock generation circuit for use with an analog delay circuits and more particularly to an analog delay circuit which delays an analog signal by repetitively performing writing/reading of information in a predetermined write/read cycle into and from memory capacitors of memory cells arranged two-dimensionally in a matrix and a clock generation circuit for use with an analog delay circuit.
2. Description of the Related Arts
A delay circuit for an analog signal is required to delay a color signal by 1 H (horizontal sweep period), for example, in a color signal demodulation circuit of a color television receiver of the PAL (Phase Alternation by Line) system. In particular, in the PAL system, since a modulated signal from two color signals is transmitted reversing the polarity thereof for each one scanning line, the color signal demodulation circuit requires a 1 H delay time in order to establish line correlations. The analog delay circuit has, for example, such a circuit construction as shown in FIG. 1.
Referring to FIG. 1 a write switch S1 and a read switch S2 are connected in series between a circuit input terminal 6 and the inverting (-) input terminal of an operational amplifier A1. The non-inverting (+) input terminal of the operational amplifier A1 is grounded, and the output terminal of the operational amplifier A1 is connected to a circuit output terminal 7, and a read capacitor Co and a reset switch S3 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier A1. Further, N selection switches S(N) and N memory capacitors C(n) are connected between a junction P of the switches S1 and S2 and the ground.
FIG. 2 is a timing chart of operations of the switches S1 to S3. Referring to FIG. 2, within a period T1, the write switch S1 and the reset switch S3 are open and the read switch S2 is closed, and consequently, charge of the nth memory capacitor C(n) is transferred to the read capacitor Co. The charge in this instance is charge which was written during the immediately preceding cycle (N clocks). Within another period T2, the read switch S2 is open and the write switch S1 and the reset switch S3 are closed. The write switch S1 writes an input signal to the circuit input terminal 6 into the memory capacitors C(n), and the reset switch S3 resets the read capacitor Co. Similarly, within a further period T3, the charge of the memory capacitor C(n+1) is read out, and within a still further period T4, the input signal is written.
FIG. 3 is a diagrammatic view of the concept of an analog delay. Referring to FIG. 3, n memory capacitors Cn are arranged, and information written in the last cycle into the ith memory capacitor Ci is read out and then information in the present cycle is written into the memory capacitor Ci. Such operation is successively performed for Ci.fwdarw.Ci+1.fwdarw. . . . .fwdarw.Cn and then for C1. Here, if the read/write cycle is represented by T, a delay of nT is produced between the written information and the read information. Therefore, a delay circuit for an analog signal can be realized in which the delay is a multiple of T.
FIG. 4 is a circuit diagram showing a detailed construction of an analog value memory circuit which includes memory capacitors C(n) and selection switches S(N). Referring to FIG. 4, memory cells formed from selection switches Smn and memory capacitors Cmn connected in series between row lines RLn and the ground are arranged in a matrix of u columns and v rows. The selection switches S11 to Su1, S12 to Su2, . . . , and S1v to Suv of the u.multidot.v memory cells are selectively controlled by column selection signals X1 to Xu outputted from an X direction scanning circuit 11 and row selection signals Y1 to Yv outputted from a Y direction scanning circuit 12.
Those selection switches S11 to Su1, S12 to Su2, . . . , S1v to Suv can be formed from MOSFETS, JFETs (junction type FETS) or bipolar transistors. A construction of memory cells of i columns and j rows where, for example, MOSFETs are used for the selection switches is shown in FIG. 5. Referring to FIG. 5, the anode of a diode Dij and a terminal of a resistor Rij are connected to the gate electrode of a MOSFET Qij serving as a selection switch. A column selection signal Xi is applied to the other terminal of the register Rij and a row selection signal Yj is applied to the cathode of the diode Dij, and only when both of the column selection signal Xi and the row selection signal Yj have a high potential, read/write from/into the memory cell Cij is enabled.
Operation waveforms of the circuit of FIG. 4 are shown in FIG. 6. Referring to FIG. 6, XCLK denotes a clock signal to be inputted to the X direction scanning circuit 11, YCLK denotes a clock signal to be inputted to the Y direction scanning circuit 12, X1 to Xu denote column selection signals, and Y1 to Y3 denote row selection signals. It is to be noted that the clock signal YCLK has a period equal to u times that of the clock signal XCLK, and within one cycle of the clock signal YCLK, reading/writing is performed from the first to the nth columns. After the one period comes to an end, the row for reading/writing changes from the jth row to the j+lth row, and then reading/writing is performed from the first to the uth columns similarly.
Here, operation for the jth row will be described with reference to a waveform diagram of FIG. 7. It is to be noted that enlarged waveforms of the row selection signal Yj and the column selection signals X1, X2 and Xu are shown in FIG. 7. First, for the memory cells in the first column, the column selection signal X1 and the row selection signal Y1 rise simultaneously. On the other hand, for the memory cells in the uth column, the column selection signal Xu and the row selection signal Yj fall simultaneously. For the memory cells in the second to (u-1)th columns, the row selection signal Yj is in a steady state, and a selection operation is performed only in response to the column selection signals X2 to Xu-1.
In other words, the first column, the uth column and the other columns are driven in different conditions from one another. Accordingly, the gate electrode waveform of the MOSFET Qij as the selection switch shown in FIG. 5 is not exactly same among the first row, the uth row and the other rows. This is because the column selection signals X1 to Xu and the row selection signals Y1 to Yv are delicately different in waveform or delay time and the diode Dij and the resistor Rij shown in FIG. 5 have parasitic capacitances and so forth.
FIG. 8 illustrates parasitic capacitances of a MOSFET in an example of the related arts wherein, for example, a MOSFET is used as a selection switch. Such parasitic capacitances Cgs, Cgd, Css and Cds as seen in FIG. 8 are present between the source and drain which are poles of the switch and the gate and a substrate (or well). Where those capacitances Cgs, Cgd, Css and Cds are very small with a single switch, a total value of parasitic capacitances of 100 to 1,000 switches amounts to 10 times or occasionally to 100 times the memory capacitors C(n). This problem similarly applies even where the switch element is formed from a JFET or a bipolar transistor although some difference is present in the structure in which the parasitic capacitances are formed.
Subsequently, it will be described what bad influence such parasitic capacitances have on the operation of an analog delay circuit. The influence of the parasitic capacitances vary a little depending upon the structure of the analog delay circuit and/or the type of switch elements, and this will be described below by way of an example of the circuit of FIG. 6. FIG. 9 shows an analog delay circuit which includes a single capacitor Cm and a single selection switch Sm in place of the N memory capacitors C(n) and selection switches S(N) of FIG. 6, respectively, and additionally includes a parasitic capacitance Cp.
The first problem resides in that, in a case wherein a charge written in the last cycle is read out is considered, an input voltage written immediately prior to that moment is stored in the parasitic capacitance Cp. As a result, the charge read out to the read capacitor Co is the sum of the original charge accumulated in the memory capacitor Cm and the charge accumulated in the parallel-connected parasitic capacitance Cp. The charge of the memory capacitor Cm has undergone a predetermined delay whereas the charge of the parasitic capacitance Cp has undergone little delay. Accordingly, the parasitic capacitance Cp gives rise to a side effect of leaking a signal free from a delay to the output.
One of possible countermeasures against the side effect is to control the individual switches at somewhat complicated timings to effect the desired compensation. In particular, it is required to prevent the side effect described above by performing such complicated timing control as to set a time for discharging the charge of the parasitic capacitance Cp by closing the reset switch S3 and the read switch S2 before the charge of the memory capacitor Cm is read out.
Another problem, which is more fatal, resides in that the settling time of the output is extended. Where the bandwidth of the operational amplifier A1 is represented by .omega.o, the response time to a step input in a full feedback condition is .tau.=1/.omega.o. However, if the parasitic capacitance Cp is present, then the feedback ratio .beta. is given by EQU .beta.=1/(1+Cp/Co) (1)
Thus, the bandwidth of the loop decreases to .beta. .omega.o and also the time constant of the transient response changes to .tau.'=1/.beta..multidot..tau.. Accordingly, if the capacitance value of the parasitic capacitance Cp is high, then this remarkably decreases the feedback ratio of the operational amplifier A1 when the charge accumulated in the memory capacitor Cm is read out, which makes high speed reading out difficult. In order to eliminate this, the bandwidth of the operational amplifier A1 should be designed to be very wide. This, however, is not practical.
In the analog delay circuit of the related art described above, when the memory cells of the matrix are scanned to select them, since such raster scanning as scanning of a television signal is performed as indicated by the arrow marks in FIG. 10, where the gate electrode waveform of the MOSFET Qij is different among the first column, the uth column and the other columns, the difference in gate electrode waveform appears as a difference in gain of the input/output characteristics in writing/reading or in offset characteristic via parasitic capacitances of the MOSFETs or arising from delicate differences in conducting state. Or in other words, there is a problem that noise of a fixed pattern is produced.
By the way, in such an application, as an application of an analog delay circuit, wherein an echo is applied, for example, to an audio signal, a high degree of accuracy is not required for the delay time. On the other hand, in a color signal demodulation circuit for a color television receiver of the PAL system, a delay time which conforms exactly with a horizontal synchronizing period is required. An example of a construction of a clock generation circuit in such an application as just described is shown in FIG. 11.
Referring to FIG. 11, the clock generation circuit shown has a PLL (Phase Locked-Loop) circuit construction which includes a voltage controlled oscillator 21, a divider 22 for dividing the oscillation frequency of the voltage controlled oscillator 21 to 1/u, a divider 23 for further dividing the division frequency of the divider 22 to 1/v, and a phase comparator 24 for comparing the phase of the division frequency of the divider 23 and a horizontal synchronizing frequency FH with each other and supplying the phase difference output thereof as a control input to the voltage controlled oscillator 21. The voltage controlled oscillator 21 is locked with an oscillation frequency equal to u.times.v times with reference to the horizontal synchronizing frequency FH to obtain a clock signal XCLK for the X direction scanning circuit 11, and the clock signal XCLK is divided to 1/u to obtain a clock signal YCLK for the Y direction scanning circuit 12.
However, with the clock generation circuit of the construction described above, since a large number of counters are required to construct the PLL circuit, there is a problem that, where the clock generation circuit is formed into an IC, the counters occupy a large area of the chip or consume substantial current. Further, where the phase difference between the clock signal XCLK and the clock signal YCLK is large, this increases the fixed pattern noise mentioned above. In order to keep the phases of the two clock signals exactly, such a countermeasure as to form the dividers 22 and 23 from synchronous counters or to latch the outputted clock signals XCLK and YCLK to synchronize them is required.